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ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Data Sheet October 15, 2008 FN9005.10
Power Sequencing Controllers
The Intersil ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128 and ISL6130 are integrated four channel controlled-on/controlled-off power-supply sequencers with supply monitoring, fault protection and a "sequence completed" signal (RESET). For larger systems, more than four supplies can be sequenced by simply connecting a wire between SYSRESET pins of cascaded IC's. The ISL6125 uses four open-drain outputs to control the on/off sequencing of four supplies, while the other sequencers use a patented, micropower 7x charge pump to drive four external low-cost NFET switch gates above the supply rail by 5.3V. These IC's can be biased from any supply 5V down to 1.5V. Individual product descriptions follow. The four channel ISL6123 (ENABLE input), ISL6124 (ENABLE input) and ISL6125 ICs offer the designer 4 rail control when it is required that all four rails are in minimal compliance prior to turn on and that compliance must be maintained during operation. The ISL6123 and ISL6130 have a low power standby mode when disabled, suitable for battery powered applications. The ISL6125 operates like the ISL6124 but instead of charge pump driven gate drive outputs it has open drain logic outputs for direct interface to other circuitry. In contrast to the majority, for both the ISL6126 and ISL6130 each of the four channels operate independently so that the various GATEs will turn on once its individually associated input voltage requirements are met. The ISL6127 is a pre-programmed A-B-C-D turn-on and D-C-B-A turn-off sequenced IC. Once all inputs are in compliance and ENABLE is asserted, the sequencing starts and each subsequent GATE will turn-on after the previous one completes turning-on. The ISL6128 has two groups of two channels each with its independent I/O and is ideal for voltage sequencing into redundant capability loads as all four inputs need to be satisfied prior to turn on but a single group fault is ignored by the other group. External resistors provide flexible voltage threshold programming of monitored rail voltages. Delay and sequencing are provided by external capacitors for both ramp-up and ramp-down. Additional I/O is provided indicating and driving RESET state in various configurations. For volume applications, other programmable options and features can be had. Contact the factory with your needs.
Features
* Enables Arbitrary Turn-on and Turn-off Sequencing of Up to Four Power Supplies (0.7V to 5V) * Operates From 1.5V to 5V Supply Voltage * Supplies VDD +5.3V of Charge Pumped Gate Drive * Adjustable Voltage Slew Rate for Each Rail * Multiple Sequencers Can be Daisy-Chained to Sequence an Infinite Number of Independent Supplies * Glitch Immunity * Undervoltage Lockout for Each Supply * 1A Sleep State (ISL6123, ISL6130) * Active High (ISL6123, ISL6130) or Low (ISL6124, ISL6125, ISL6126, ISL6127, ISL6128) ENABLE Input * Open Drain Version Available (ISL6125) * Voltage Determined Sequence (ISL6126, ISL6130) * Pre-programmed Sequence Available (ISL6127) * Dual Channel Groupings (ISL6128) * QFN Package * Pb-Free Available (RoHS compliant)
Applications
* Graphics Cards * FPGA/ASIC/microprocessor/PowerPC Supply Sequencing * Network Routers * Telecommunications Systems
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2001, 2003-2008. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130 Ordering Information
PART NUMBER (Note 1) ISL6123IR ISL6124IR ISL6125IR ISL6126IR ISL6127IR ISL6128IR ISL6123IRZA (Note 2) ISL6124IRZA (Note 2) ISL6125IRZA (Note 2) ISL6126IRZA (Note 2) ISL6127IRZA (Note 2) ISL6128IRZA (Note 2) ISL6130IRZA (Note 2) ISL612XSEQEVAL1Z ISL6125EVAL1Z NOTES: 1. Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PART MARKING ISL 6123IR ISL 6124IR ISL 6125IR ISL 6126IR ISL 6127IR ISL 6128IR 61 23IRZ 61 24IRZ 61 25IRZ 61 26IRZ 61 27IRZ 61 28IRZ 61 30IRZ TEMP. RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE 24 Ld 4x4 QFN 24 Ld 4x4 QFN 24 Ld 4x4 QFN 24 Ld 4x4 QFN 24 Ld 4x4 QFN 24 Ld 4x4 QFN 24 Ld 4x4 QFN (Pb-free) 24 Ld 4x4 QFN (Pb-free) 24 Ld 4x4 QFN (Pb-free) 24 Ld 4x4 QFN (Pb-free) 24 Ld 4x4 QFN (Pb-free) 24 Ld 4x4 QFN (Pb-free) 24 Ld 4x4 QFN (Pb-free) PKG. DWG. # L24.4x4 L24.4x4 L24.4x4 L24.4x4 L24.4x4 L24.4x4 L24.4x4 L24.4x4 L24.4x4 L24.4x4 L24.4x4 L24.4x4 L24.4x4
ISL612X Pb Free Evaluation Platform ISL6125 Pb Free Evaluation Platform
AIN BIN CIN DIN
AOUT BOUT COUT
VDD
BIAS LOCK OUT
VDD+5V Q-PUMP
1A
DOUT
1A DLY_ONX
GATE D GATE C GATE B GATE A DIN CIN BIN AIN
VDD ENABLE SYSRST RESET GROUND DLY_OFF_A DLY_OFF_B DLY_OFF_C
UVLO_A UVLO_B UVLO_C UVLO_D DLY_OFF_D
1.26V
1A
-1A
DLY_ON_A
DLY_ON_B
DLY_ON_C
DLY_ON_D
DLY_OFFX
10ms RISING DELAY 1.26V 30s FILTER UVLOX LOGIC 0.633V EN SYSRST 150ms RISING DELAY RESET GATEX
FIGURE 1. TYPICAL ISL6123 APPLICATION USAGE
FIGURE 2. ISL6123 BLOCK DIAGRAM (1/4)
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FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130 Pinouts
ISL6123, ISL6124, ISL6125 (24 LD QFN) TOP VIEW
DLY_ON_A UVLO_A SYSRST RESET RESET
ISL6127 (24 LD QFN) TOP VIEW
UVLO_A 20 SYSRST
VDD
VDD
NC
NC
24 ENABLE_1/ ENABLE_1 GATE_A DLY_OFF_C DLY_OFF_D GATE_B GATE_C 1 2 3 4 5 6 7 GATE_D
23
22
21
20
19 18 DLY_OFF_A 17 UVLO_C 16 DLY_ON_C ENABLE_1/ ENABLE_1 GATE_A NC NC GATE_B GATE_C 1 2 3 4 5 6
24
23
22
21
19 18 NC 17 UVLO_C 16 NC
EPAD (GND)
15 DLY_ON_D 14 UVLO_D 13 DLY_OFF_B
EPAD (GND)
NC 15 NC 14 UVLO_D 13 NC 12 UVLO_B 19 18 DLY_OFF_A 17 UVLO_C 16 DLY_ON_C NC 15 DLY_ON_D 14 UVLO_D 13 DLY_OFF_B 12 UVLO_B
8 DLY_ON_B
9 NC
10 GND
11 NC
12 UVLO_B
7 GATE_D
8 NC
9 NC
10 GND DLY_ON_A 21 10 GND
11 NC 20 11 ENABLE_2 UVLO_A
ISL6126, ISL6130 (24 LD QFN) TOP VIEW
UVLO_A RESET
ISL6128 (24 LD QFN) TOP VIEW
RESET
VDD
VDD 23 8 DLY_ON_B
NC
NC
NC
24 ENABLE_1/ ENABLE_1 GATE_A DLY_OFF_C DLY_OFF_D GATE_B GATE_C 1 2 3 4 5 6 7 GATE_D
23
22
21
20
19 18 DLY_OFF_A 17 UVLO_C 16 NC ENABLE_1 GATE_A DLY_OFF_C DLY_OFF_D GATE_B GATE_C 1 2 3 4 5 6
24
22
EPAD (GND)
15 NC 14 UVLO_D 13 DLY_OFF_B
8 NC
9 NC
10 GND
11 NC
12 UVLO_B
7 GATE_D
9 RESET_2
3
NC
EPAD (GND)
FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130 Pin Descriptions
PIN NUMBER PIN NAME VDD GND ENABLE_1/ ENABLE_1 ENABLE_2/ ENABLE_2 ISL6123, ISL6124, ISL6125 23 10 1 NC ISL6126, ISL6130 23 10 1 NC ISL6127 23 10 1 NC ISL6128 23 10 1 11 DESCRIPTION Chip Bias. Bias IC from nominal 1.5V to 5V Bias Return. IC ground Input to start on/off sequencing. Input to initiate the start of the programmed sequencing of supplies on or off. Enable functionality is disabled for 10ms after UVLO is satisfied. ISL6123 and ISL6130 have ENABLE. ISL6124, ISL6125, ISL6126 and ISL6127 have ENABLE. Only ISL6128 has 2 ENABLE inputs; 1 for each 2 channel grouping. ENABLE_1 for (A, B), and ENABLE_2 for (C, D). RESET Output. RESET provides a low signal 150ms after all GATEs are fully enhanced. This delay is for stabilization of output voltages. RESET will assert low upon UVLO not being satisfied or ENABLE/ENABLE being deasserted. The RESET outputs are open drain N-channel FET and is guaranteed to be in the correct state for VDD down to 1V and is filtered to ignore fast transients on VDD and UVLO_X. RESET_2 only exists on ISL6128 for (C, D) group I/O. Undervoltage Lock Out/Monitoring Input. These inputs provide for a programmable UV lockout referenced to an internal 0.633V reference and are filtered to ignore short (<30s) transients below programmed UVLO level.
RESET RESET_2
24 NC
24 NC
24 NC
24 9
UVLO_A UVLO_B UVLO_C UVLO_D DLY_ON_A DLY_ON_B DLY_ON_C DLY_ON_D DLY_OFF_A DLY_OFF_B DLY_OFF_C DLY_OFF_D GATE_A GATE_B GATE_C GATE_D SYSRST
20 12 17 14 21 8 16 15 18 13 3 4 2 5 6 7 22
20 12 17 14 18 13 3 4 2 5 6 7 -
20 12 17 14 2 5 6 7 22
20 12 17 14 21 8 16 15 18 13 3 4 2 5 6 7 -
Gate On Delay Timer Output. Allows for programming the delay and sequence for VOUT turn-on using a capacitor to ground. Each capacitor is charged with 1A, 10ms after turn-on initiated by ENABLE/ENABLE with an internal current source providing delay to the associated FETs GATE turn-on.
Gate Off Delay Timer Output. Allows for programming the delay and sequence for VOUT turn-off through ENABLE/ENABLE via a capacitor to ground. Each capacitor is charged with a 1A internal current source to an internal reference voltage causing the corresponding gate to be pulled down turning-off the FET. FET Gate Drive Output. Drives the external FETs with a 1A current source to soft-start ramp into the load. On the ISL6125 only, these are open drain outputs that can be pulled up to a maximum of VDD voltage.
System Reset I/O. As an input, allows for immediate and unconditional latch-off of all GATE outputs when driven low. This input can also be used to initiate the programmed sequence with `zero' wait (no 10ms stabilization delay) from input signal on this pin being driven high to first GATE. As an output when there is a UV condition, this pin pulls low. If common to other SYSRST pins in a multiple IC configuration, it will cause immediate and unconditional latch-off of all other GATEs on all other ISL612X sequencers. Ground. Die Substrate No Connect
GND NC
EPAD 9, 19
EPAD 8, 9, 11, 15, 16, 19, 21, 22
EPAD 3, 4, 8, 9, 11, 13, 15,16,18, 19, 21
EPAD 19, 22
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FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130 ISL612X Variant Feature Matrix
NUMBER OF NUMBER OF CHANNELS UVLO THAT INPUTS TURN-OFF GATE DRIVE REQUIRED WHEN 1 OR OPEN CONDITIONS MONITORED BY EACH FOR INITIAL UVLO DRAIN CMOS/ RESET START-UP FAULTS OUTPUTS TTL TTL Gate Drive 4 UVLO 1 EN 4 UVLO 1 EN 4 UVLO 1 EN 1 UVLO 1 EN 4 UVLO 4 Gates
PART NAME ISL6123
EN/EN EN
PRESET OR ADJUSTABLE SEQUENCE
NUMBER OF UVLO AND PAIRS OF I/O
FEATURES
Time Adjustable 4 Monitors with Auto Restart, On and Off 1 I/O Low Bias Current Sleep Time Adjustable 4 Monitors with Auto Restart On and Off 1 I/O
ISL6124 ISL6125
EN EN
CMOS CMO
Gate Drive Open Drain
4 UVLO 4 UVLO
4 Gates
4 Open Drain Time Adjustable 4 Monitors with Auto Restart, Open On and Off 1 I/O Drain Sequenced Outputs 1 Gate 4 Monitors with Gates Independent Voltage 1 I/O On as UVLO Valid Determined ON Time Adjustable Off Preset Preset 4 Monitors with Auto Restart 1 I/O 2 Monitors with Dual Redundant 2 I/O Operation Gates Independent On as UVLO Valid Low Bias Current Sleep
ISL6126
EN
CMOS
Gate Drive
4 UVLO
ISL6127 ISL6128 ISL6130
EN EN EN
CMOS CMOS TTL
Gate Drive Gate Drive Gate Drive
4 UVLO 1 EN 4 UVLO 2 EN 1 UVLO 1 EN
4 UVLO 2 UVLO 4 UVLO
4 Gates 2 Gates 1 Gate
4 Monitors with Voltage 1 I/O Determined ON Time Adjustable Off
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FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Absolute Maximum Ratings
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+6V ISL6125 LOGIC OUT. . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V UVLO, ENABLE, ENABLE, SYSRST . . . . . . . . -0.3V to VDD + 0.3V RESET, DLY_ON, DLYOFF . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
Thermal Information
Thermal Resistance (Typical, Notes 3, 4) JA (C/W) JC (C/W) 24 Ld 4x4 QFN Package . . . . . . . . . . . 48 9 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +125C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . +1.5V to +5.5V Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 5. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
VDD = 1.5V to +5V, TA = TJ = -40C to +85C, unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
PARAMETER UVLO Falling Undervoltage Lockout Threshold Undervoltage Lockout Threshold Tempco Undervoltage Lockout Hysteresis Undervoltage Lockout Threshold Range Undervoltage Lockout Delay Transient Filter Duration DELAY ON/OFF Delay Charging Current Delay Charging Current Range Delay Charging Current Temperature Coefficient Delay Threshold Voltage Delay Threshold Voltage Temperature Coefficient ENABLE/ENABLE, RESET AND SYSRST I/O ENABLE Threshold ENABLE Threshold ENABLE/ENABLE Hysteresis ENABLE/ENABLE Lockout Delay ENABLE/ENABLE Input Capacitance RESET Pull-up Voltage RESET Pull-Down Current
VUVLOvth TCUVLOvth VUVLOhys RUVLOvth TUVLOdel tFIL
TJ = +25C
619
633 40 10
647
mV nV/C mV mV ms s
Max VUVLOvth- Min VUVLOvth ENABLE satisfied VDD, UVLO, ENABLE glitch filter
7 10 30
DLY_ichg DLY_ichg_r TC_DLY_ichg DLY_Vth TC_DLY_Vth
VDLY = 0V DLY_ichg(max) - DLY_ichg(min)
0.92
1 0.08 0.2
1.08
A A nA/C
1.238
1.266 0.2
1.294
V mV/C
VENh VENh VENh -VENl tdelEN_LO Cin_en Vpu_rst IRSTpd1 IRSTpd3 IRSTpd5 VDD = 1.5V, RST = 0.1V VDD = 3.3V, RST = 0.1V VDD = 5V, RST = 0.1V GATE = VDD+5V Measured at VDD = 1.5V UVLO satisfied
1.2 0.5 VDD 0.2 10 5 VDD 5 13 17 160
V V V ms pF V mA mA mA ms
RESET Delay after GATE High
TRSTdel
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FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Electrical Specifications
VDD = 1.5V to +5V, TA = TJ = -40C to +85C, unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL VRSTl COUT_RST Vpu_srst Ipu_1.5 Ipu_5 SYSRST Low Output Voltage SYSRST Output Capacitance SYSRST Low to GATE Turn-Off GATE GATE Turn-On Current GATE Turn-Off Current GATE Current Range GATE Turn-On/Off Current Temperature Coefficient GATE Pull-Down High Current GATE High Voltage IGATEon IGATEoff_l IGATE_range TC_IGATE IGATEoff_h VGATEh VGATEh GATE Low Voltage BIAS IC Supply Current IVDD_5V IVDD_3.3V IVDD_1.5V ISL6123, ISL6130 Stand By IC Supply Current VDD Power-on Reset IVDD_sb VDD_POR VDD = 5V VDD = 3.3V VDD = 1.5V VDD = 5V, ENABLE = 0V 0.20 0.14 0.10 1 1 0.5 mA mA mA A V VGATEl GATE = VDD, UVLO = 0V VDD < 2V, TJ = +25C VDD > 2V Gate Low Voltage, VDD = 1V VDD + 5V GATE = 0V GATE = VDD, Disabled Within IC IGATE max-min 0.2 88 VDD + 4.9V VDD + 5.3V 0 0.1 0.8 -1.4 1.1 -1.05 1.4 -0.8 0.35 A A A nA/C mA V V V Vol_srst Cout_srst tdelSYS_G GATE = 80% of VDD + 5V VDD = 1.5V VDD = 5V VDD = 1.5V, IOUT = 100A TEST CONDITIONS Measured at VDD = 5V with 5k pull-up resistors 10 VDD 5 100 150 10 40 MIN TYP MAX 0.1 UNIT V pF V A A mV pF ns
PARAMETER RESET Output Low RESET Output Capacitance SYSRST Pull-Up Voltage SYSRST Pull-Down Current
Descriptions and Operation
The ISL612X sequencer family consists of several four channel voltage sequencing controllers in various functional and personality configurations. All are designed for use in multiple-voltage systems requiring power sequencing of various supply voltages. Individual voltage rails are gated on and off by external N-Channel MOSFETs, the gates of which are driven by an internal charge pump to VDD + 5.3V (VQP) in a user programmed sequence. With the four-channel ISL6123 the ENABLE must be asserted high and all four voltages to be sequenced must be above their respective user programmed Undervoltage Lock Out (UVLO) levels before programmed output turn on sequencing can begin. Sequencing and delay determination is accomplished by the choice of external capacitor values on the DLY_ON and DLY_OFF pins. Once all four UVLO inputs and ENABLE are satisfied for 10ms, 7
the four DLY_ON capacitors are simultaneously charged with 1A current sources to the DLY_Vth level of 1.27V. As each DLY_ON pin reaches the DLY_Vth level its associated GATE will then turn-on with a 1A source current to the VQP voltage of VDD + 5.3V. Thus, all four GATEs will sequentially turn-on. Once at DLY_Vth the DLY_ON pins will discharge to be ready when next needed. After the entire turn on sequence has been completed and all GATEs have reached the charge pumped voltage (VQP), a 160ms delay is started to ensure stability after which the RESET output will be released to go high. Subsequent to turn-on, if any input falls below its UVLO point for longer than the glitch filter period (~30s) this is considered a fault. RESET and SYSRST are pulled low and all GATEs are simultaneously also pulled low. In this mode the GATEs are pulled low with 88mA. Normal shutdown mode is entered when no UVLO is violated and the ENABLE is deasserted. When ENABLE is deasserted, RESET is
FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
asserted and pulled low. Next, all four shutdown ramp capacitors on the DLY_OFF pins are charged with a 1A source and when any ramp-capacitor reaches DLY_Vth, a latch is set and a current is sunk on the respective GATE pin to turn off its external MOSFET. When the GATE voltage is approximately 0.6V, the GATE is pulled down the rest of the way at a higher current level. Each individual external FET is thus turned off removing the voltages from the load in the programmed sequence. The ISL6123 and ISL6124 have the same functionality except for the ENABLE active polarity with the ISL6124 having an ENABLE input. Additionally, the ISL6123 and ISL6130 also have an ultra low power sleep state when ENABLE is low. The ISL6125 has the same personality as the ISL6124 but instead of charged pump driven GATE outputs it has open drain outputs that can be pulled up to a maximum of VDD. The ISL6126 and ISL6130 are different in that their sequence on is not time determined but voltage determined. Each of the four channels operates independently so that once the IC is biased and any one of the UVLO inputs is greater than the 0.63V internal reference, the enable input is also satisfied and the GATE for the associated UVLO input will turn-on. In turn, the other UVLO inputs need to be satisfied for the associated GATEs to turn-on. 150ms after all GATEs are fully on (GATE voltage = VQP), the RESET is released to go high. The UVLO inputs can be driven by either a previously turned on output rail offering a voltage determined sequence or by logic signal inputs. Any subsequent UVLO level < its programmed level will pull the associated GATE and RESET output low (if previously released), but will not latch-off the other GATEs. Predetermined turn-off is accomplished by deasserting enable, this will cause RESET to latch low and all four GATE outputs to follow the programmed turn off sequence similar to ISL6124. The ISL6127 is a four-channel sequencer pre-programmed for A-B-C-D turn-on and D-C-B-A turn-off. After all four UVLO and ENABLE inputs are satisfied for ~10ms, the sequencing starts and the next GATE in the sequence starts to ramp-up once the previous GATE has reached ~VQP-1V. 160ms after the last GATE is at VQP, the RESET output will be deasserted. Once any UVLO is unsatisfied, RESET is pulled low, SYSRST is pulled low and all GATEs are simultaneously turned off. When ENABLE is signaled high the D GATE will start to pull low and once below 0.6V the next GATE will then start to pull low and so on until all GATEs are at 0V. Unloaded, this turn off sequence will complete in <1ms. This variant offers a lower cost and size implementation as the external delay capacitors are not used. Since the delay capacitors are not used, this IC cannot delay the start of subsequent GATEs, thus necessary stabilization or system house keeping need to be considered. 8 The ISL6128 is a four-channel device that groups the four channels into two groups of two channels each, as A, B and C, D, each group having its own ENABLE and RESET I/IO pins. This requires all four UVLO and both ENABLEs to be satisfied for sequencing to start. The A, B group will first turn on 10ms after the second ENABLE is pulled low with A then B turning on followed by C then D. Once the preceding GATE = VQP the next DLY_ON pin starts to charge its capacitor thus turning on all four GATEs. Approximately 160ms after D GATE = VQP the RESET output is released to go high. Once any UVLO is unsatisfied, only the related group's RESET and two GATEs are pulled low. The related EN input has to be cycled for the faulted group to be turned-on again. Normal shutdown is invoked by either signaling both ENABLE inputs high which will cause all the two related GATEs to shutdown in reverse order from turn-on. DLY_X capacitors adjust the delay between GATES during turn on and off but not the order. During bias up the RESET output is guaranteed to be in the correct state with VDD lower than 1V. The SYSRST pin follows the VDD upon power-up with a weak internal pull-up and is both an input and output connection providing two functions. As an input, if it is pulled low, all GATEs will be unconditionally shut off and RESET pulls low, (see Figure 7). This input can also be used as a no wait enabling input, if all inputs (ENABLE and UVLO) are satisfied, it does not wait through the ~10ms enable delay to initiate DLY_ON capacitor charging when released to go high. As an output, it is useful when implementing multiple sequencers in a design needing simultaneous shutdown as with a kill switch across all sequencers. Once any UVLO is unsatisfied longer than tFIL the related SYSRST will pull low and pull all other SYSRST inputs low that are on a common connection thus unconditionally shutting down all outputs across multiple sequencers. Except for the ISL6128 after a fault, restart of the turn-on sequence is automatic once all requirements are met. This allows for no interaction between the sequencer and a controller IC if desired. The ENABLE and RESET I/O do allow for a higher level of feedback and control if desired. The ISL6128 requires that the related ENABLE be cycled for restart of its associated group GATEs. If no capacitors are connected between DLY_ON or DLY_OFF pins and ground then all such related GATEs start to turn on immediately after the 10ms (TUVLOdel) ENABLE stabilization time out has expired and the GATEs start to immediately turn off when ENABLE is asserted. If some of the rails are to be sequenced together in order to eliminate the effect of capacitor variance on the timing and to reduce cost, a common capacitor can be connected to two or more DLY_ON or DLY_OFF pins. In this case multiply the capacitor value by the number of common DLY_X pins to retain the desired timing. Table 1 illustrates the nominal time delay from the start of
FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
charging to the 1.27V reference for various capacitor values on the DLY_X pins. This table does not include the 10ms of enable lock out delay during a start-up sequence but represents the time from the end of the enable lock out delay to the start of GATE transition. There is no enable lock out delay for a sequence off, so this table illustrates the delay to GATE transition from a disable signal.
TABLE 1. NOMINAL DELAY TO SEQUENCING THRESHOLD DLY PIN CAPACITANCE Open 100pF 1000pF 0.01F 0.1F 1F TIME(s) 0.00006 0.00013 0.0013 0.013 0.13 1.3 TABLE 1. NOMINAL DELAY TO SEQUENCING THRESHOLD DLY PIN CAPACITANCE 10F TIME(s) 13
NOTE: Nom. TDEL_SEQ = Capacitor (F)*1.3M.
Figure 3 illustrates the turn-on and Figure 4 illustrates the nominal turnoff timing diagram of the ISL6123 and ISL6124 product. The ISL6125 is similar to the ISL6124 except that instead of charge pumped GATE outputs, there are sequenced open drain outputs that can be pulled up to a maximum of VDD. Note the delay and flexible sequencing possibilities. Multiple series, parallel or adjustable capacitors can be used to easily fine tune timing between that offered by standard value capacitors.
l
VUVLOVth UVLO_A VUVLOVth UVLO_B VUVLOVth UVLO_C VUVLOVth UVLO_D ENABLE (ISL6124) ENABLE (ISL6123) tUVLOdel VEN DLY_Vth DLYON_B DLY_Vth DLYON_D DLY_Vth DLYON_A DLYON_C DLY_Vth
VQPUMP VQPUMP GATE_B GATE_D GATE_C GATE_A VQPUMP-1V tRSTdel VQPUMP VQPUMP
RESET
FIGURE 3. ISL6123, ISL6124 TURN-ON AND GLITCH RESPONSE TIMING DIAGRAM
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FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
UVLO_X>VUVLOVth ENABLE (ISL6123) ENABLE (ISL6124) DLYOFF_A DLY_Vth DLYOFF_B DLY_Vth DLYOFF_C DLY_Vth DLYOFF_D VEN DLY_Vth
GATE_C GATE_D GATE_A
GATE_B RESET
FIGURE 4. ISL6123, ISL6124 TURN-OFF TIMING DIAGRAM
Typical Performance Curves
634 DLY CURRENT SOURCE (A) 633 VDD = 5V UV THRESHOLD (mV) 632 631 630 629 628 627 626 -40 VDD = 1.5V 1.04 1.03 1.02 1.01 1.00 0.99 DLY_OFF/ON 0.98 0.97 -40 VDD = +5V -20 0 20 40 60 80 100 VDD = 1.5V
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 5. UVLO THRESHOLD VOLTAGE
FIGURE 6. DLY CHARGE CURRENT
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FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130 Typical Performance Curves
(Continued)
GATE
5VOUT 3.3VOUT
SYSRST
2V/DIV
1s/DIV
FIGURE 7. SYSRST LOW TO OUTPUT LATCH OFF
Using the ISL612XSEQEVAL1Z Platform
The ISL612XSEQEVAL1Z platform is the primary evaluation board for this family. The board has two complete, separate and electrically identical circuits. See Figure 16 for its schematic and photograph. Additionally, there is an ISL6125 specific evaluation platform, ISL6125EVAL1Z, due to its unique open drain outputs for ease of evaluation. See Figure 17 for its schematic and photograph. In the top right hand corner of the board is a SMD layout with ISL6123 illustrating the full functionality and small implementation size for an application having the highest component count. The majority of the board is given over to a socket and discrete through-hole components circuit for ease of evaluation flexibility through IC variant swapping and modification of UVLO levels and sequencing order by passive component substitution. The board is shipped with the ISL6123 installed in both locations and with two each of the other released variant types loose packed. As this sequencer family has a common function pinout there are no major modifications to the board necessary to evaluate the other ICs. To the left, right and above the socket are four test point strips (TP1, TP2, TP3, TP4). These give access to the labeled IC I/O pins during evaluation. Remember that significant current or capacitive loading of particular I/O pins will affect functionality and performance. Attention to orientation and placement of variant ICs in the socket must be paid to prevent IC damage or faulty evaluation.
The default configuration of the ISL612XSEQEVAL1Z circuitries was built around the following design assumptions: 1. Using the ISL6123IR or ISL6124IR 2. The four supplies being sequenced are 5V (IN_A), 3.3V (IN_B), 2.5V (IN_C) and 1.5V (IN_D), the UVLO levels are ~80% of nominal voltages. Resistors chosen such that the total resistance of each divider is ~10k using standard value resistors to approximate 80% of nominal = 0.63V on UVLO input. Resistor choice is such that I x R2 = 0.633V at the desired UV (undervoltage) level as the monitored voltage decreases. Total resistance in the divider is a factor for the designer to consider for accuracy of UV level and efficiency vs electrical noise immunity trade-offs.
VMONITORED
R1
Vmon/0.633mV = R1+R2/R2 when Vmon = desired UV level as Vmon decreases. For example, a 5V supply with a desired UV level at 4V would mean R1+R2/R2 = 6.319. Ideally, any R1 and R2 combination that met this ratio would work, but with only standard value resistors available, small deviations will occur.
UVLO R2
3. The desired order turn-on sequence is first both 5V and 3.3V supplies together and then the 2.5V supply about 75ms later and lastly, the 1.5V supply about 45ms later. 4. The desired turn-off sequence is first both 1.5V and 3.3V supplies at the same time then the 2.5V supply about 50ms later and lastly, the 5V supply about 72ms after that. All scope shots are taken from ISL612XSEQEVAL1Z board. Figures 8 and 9 illustrate the desired turn-on and turn-off sequences respectively. The sequencing order and delay
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FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
between voltages sequencing is set by external capacitance values, so other than illustrated can be accomplished. Figures 10 and 11 illustrate the timing relationships between the EN input, RESET, DLY and GATE outputs and the VOUT voltage for a single channel being turned on and off respectively. RESET is not shown in Figure 10 as it asserts 160ms after the last GATE goes high. All IC family variants share similar function for DLY_X capacitor charging, GATE and RESET operation. Figures 12 through 15 illustrate the principal feature and functional differences for each of the ISL6125, ISL6126, ISL6127 and ISL6128 variants. Figure 12 features the ISL6125 open drain outputs being sequenced on and off along with RESET relationship, which is similar to all other family variants. Figure 13 illustrates the independent input feature of the ISL6126 which allows once the EN is low for each UVLO to be individually satisfied and for its associated GATE to turn-on. Only when the last variable VIN is satisfied as shown does the RESET release to signal all input voltages are valid. Figure 14 shows the ISL6127 pre-programmed ABCD on DCBA off order of sequencing with minimal non-adjustable delay between each. Figure 15 demonstrates the independence of the redundant two rail sequencer. It shows that either one of the two groups can be turned off and the ABCD order of restart with capacitor programmable delay once both EN inputs are pulled low.
Using the ISL6125EVAL1Z Platform
The ISL6125EVAL1Z is the ISL6125 specific evaluation board providing for easy evaluation of the ISL6125 with its unique open drain outputs. The UVLO levels, sequence and delays are programmed exactly like the other ISL612X ICs but the ISL6125 has sequenced open drain outputs rather than charge pumped driven GATE outputs. See Figure 17 for its schematic and photograph.
Typical Performance Waveforms
5VOUT RESET ENABLE 3.3VOUT
5VOUT
3.3VOUT
2.5VOUT 1.5VOUT 1.5VOUT 2.5VOUT
ENABLE 1V/DIV 40ms/DIV 1V/DIV 20ms/DIV
FIGURE 8. ISL6124 SEQUENCED TURN-ON
FIGURE 9. ISL6124 SEQUENCED TURN-OFF
TdelENLO
GATE 2V/DIV
GATE 2V/DIV
3.3VO 1V/DIV DLY_Vth
3.3VO 1V/DIV RESET 2V/DIV DLY_Vth
DLY_ON 1V/DIV EN 2V/DIV 10ms/DIV
EN 2V/DIV
DLY_OFF 1V/DIV
4ms/DIV
FIGURE 10. ISL6123 SINGLE CHANNEL TURN-ON
FIGURE 11. ISL6123 SINGLE CHANNEL TURN-OFF
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FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130 Typical Performance Waveforms
EN
(Continued)
VIN_VAR
RESET
STATIC EN/ALL OTHER VOUT
VOUT_VAR LOGIC A -D SEQUENCED OUTPUTS
TRSTdel
RESET 100ms/DIV 100ms/DIV
FIGURE 12. ISL6125 LOGIC OUTPUTS SEQUENCED ON AND OFF AND RESET RELATIONSHIP
FIGURE 13. ISL6126 UVLO INPUT/OUTPUT INDEPENDENCE AND RESET RELATIONSHIP
A_VOUT
EN_1 5V/DIV EN_2 5V/DIV
B_VOUT C_VOUT A_VOUT D_VOUT B_VOUT C_VOUT D_VOUT
FIGURE 14. ISL6127 PREPROGRAMMED ABCD TURN-ON AND DCBA TURN-OFF
FIGURE 15. ISL6128 GROUP INDEPENDENT TURN-OFF AND DELAY ADJUSTABLE PRE PROGRAMMED TURN-ON
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FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
IND = +1.5V INB = +3.3V INC = +2.5V
INA AND VDD = +5V C1 1 11 23 VDD ENABLE_1DLY_ON_B ENABLE_2DLY_ON_D DLY_ON_C R1 7.681k R3 4.99k R5 6.98k R7 8.45k 12 14 17 20 R2 2.26k R4 4.99k R6 3.01k R8 1.47k DLY_ON_A S1 UVLO_B DLY_OFF_C UVLO_D DLY_OFF_D UVLO_C DLY_OFF_B UVLO_A DLY_OFF_A ISL612XIR GATE_A GATE_B GATE_C 22 SYSRST NC GATE_D RESET2 RESET1 GND 10 1F 8 C2 C6 0.1F C7 0.01F C8 0.01F C9 0.1F 2 5 6 7 20 19 9 24 1 R10 R9 750 750 4 3 2 1 5 6 SI4922DY Q3 7 8 SI4922DY Q3 4 3 56 SI4922DY SI4922DY 78 2 1 Q4
EN1 EN2
15 0.01F C3 16 21 0.068F 3 4 C4
0.047F C5 13 18 0.01F
SYSRST
Q4
RL8
10
RL7
5
RL6
5
RL5
2
Z
FIGURE 16. EVAL BOARD CHANNEL 1 SCHEMATIC AND ISL612XSEQEVAL1Z PHOTOGRAPH
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FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
2.5V_(IND) 1.5V_(INC) 3.3V_(INB) 5.0V_(INA) C1 23 ENABLE 1 ENABLE VDD DLY_ON_B DLY_ON_D DLY_ON_C 7.68k 6.98k 4.99k 8.45k R1 R2 R4 R6 DLY_ON_A 12 14 17 20 2.26k 3.01k 4.99k 1.47k U1 UVLO_B UVLO_D UVLO_C UVLO_A DLY_OFF_C DLY_OFF_D DLY_OFF_B DLY_OFF_A 8 15 16 21 3 4 13 18 2 5 6 7 1F C2 0.01F C3 0.022F C4 0.068F C5 OPEN C6 0.047F C7 OPEN C8 0.01F C9 0.1F A R12 R11 R3 R5 R8 R9 R10 R13 10k 10k 10k 10k SEQ_A SEQ_B SEQ_C SEQ_D R7 D1 750
ISL612X GATE_A
GATE_B 22 9 11 25 EP 10 GND 19 SYSRST NC NC RESET GATE_C GATE_D
SYSRST
24
RESET AGND A
FIGURE 17. ISL6125EVAL1Z SCHEMATIC AND PHOTOGRAPH
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FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
TABLE 2. ISL612XSEQEVAL1Z BOARD CHANNEL 1 COMPONENT LISTING COMPONENT DESIGNATOR S1 Q3, Q4 R7 R8 R1 R2 R5 R6 R3 R4 R9 R10 C7 C9 C2 C5 C3 C4 C6 C8 C1 D1 D2 RL8 RL7 RL6 RL5 COMPONENT FUNCTION ISL612X, 4 Supply Sequencer Socket Voltage Rail Switches 5V to UVLO_A Resistor for Divider String UVLO_A to GND Resistor for Divider String 3.3V to UVLO_B Resistor for Divider String UVLO_B to GND Resistor for Divider String 2.5V to UVLO_C Resistor for Divider String UVLO_C to GND Resistor for Divider String 1.5V to UVLO_D Resistor for Divider String UVLO_D to GND Resistor for Divider String RESET1 LED Current Limiting Resistor RESET2 LED Current Limiting Resistor 5V turn-on Delay Capacitor (13ms) 5V turn-off Delay Capacitor (130ms) 3.3V turn-on Delay Capacitor (13ms) 3.3V turn-off Delay Capacitor (3ms) 2.5V turn-on Delay Capacitor (88ms) 2.5V turn-off Delay Capacitor (61ms) 1.5V turn-on Delay Capacitor (130ms) 1.5V turn-off Delay Capacitor (13ms) Decoupling Capacitor RESET1 Indicating LED RESET2 Indicating LED 5V Load Resistor 3.3V Load Resistor 2.5V Load Resistor 1.5V Load Resistor COMPONENT DESCRIPTION Intersil, ISL612X4 Supply Sequencer Socket SI4922DY or equivalent, Dual 8A, 30V, 0.018, N-Channel MOSFET 8.45k 1%, 0402 1.47k 1%, 0402 7.68k 1%, 0402 2.26k 1%, 0402 6.98k 1%, 0402 3.01k 1%, 0402 4.99k 1%, 0402 4.99k 1%, 0402 750 10%, 0805 750 10%, 0805 0.01F 10%, 6.3V, 0402 0.1F 10%, 6.3V, 0402 0.01F 10%, 6.3V, 0402 0.01F 10%, 6.3V, 0402 0.068F 10%, 6.3V, 0402 0.047F 10%, 6.3V, 0402 0.1F 10%, 6.3V, 0402 0.01F 10%, 6.3V, 0402 0.1F, 0805 0805, SMD LEDs Red 0805, SMD LEDs Red 10 20%, 3W Carbon 5 20%, 3W Carbon 5 20%, 3W Carbon 2 20%, 3W Carbon
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FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
TABLE 3. ISL6125EVAL1Z COMPONENT LISTING COMPONENT DESIGNATOR U1 R6 R12 R1 R11 R2 R3 R4 R5 R9 C5 C9 C2 C8 C3 C7 C4 C6 C1 D1 R8 R9 R10 R13 COMPONENT FUNCTION ISL6125, Four Supply Sequencer 5V to UVLO_A Resistor for Divider String UVLO_A to GND Resistor for Divider String 3.3V to UVLO_B Resistor for Divider String UVLO_B to GND Resistor for Divider String 2.5V to UVLO_D Resistor for Divider String UVLO_D to GND Resistor for Divider String 1.5V to UVLO_C Resistor for Divider String UVLO_D to GND Resistor for Divider String RESET LED Current Limiting Resistor 5V turn-on Delay Capacitor A 5V turn-off Delay Capacitor A (135ms) 3.3V turn-on Delay Capacitor B (13.7ms) 3.3V turn-off Delay Capacitor B (13.7ms) 2.5V turn-on Delay Capacitor D (28ms) 2.5V turn-off Delay Capacitor D 1.5V turn-on Delay Capacitor C (98ms) 1.5V turn-off Delay Capacitor C (59ms) Decoupling Capacitor RESET1 Indicating LED SEQ_OUTPUT_A Pull-Up Resistor SEQ_OUTPUT_B Pull-Up Resistor SEQ_OUTPUT_C Pull-Up Resistor SEQ_OUTPUT_D Pull-Up Resistor COMPONENT DESCRIPTION Intersil, ISL6125, Four Supply Sequencer with Open Drain Outputs 8.45k 1%, 0402 1.47k 1%, 0402 7.68k 1%, 0402 2.26k 1%, 0402 6.98k 1%, 0402 3.01k 1%, 0402 4.99k 1%, 0402 4.99k 1%, 0402 750 10%, 0805 DNP, 0402 0.1F 10%, 6.3V, 0402 0.01F 10%, 6.3V, 0402 0.01F 10%, 6.3V, 0402 0.022F 10%, 6.3V, 0402 DNP, 0402 0.068F 10%, 6.3V, 0402 0.047F 10%, 6.3V, 0402 0.1F, 0805 0805, SMD LED 10k, 0402 10k, 0402 10k, 0402 10k, 0402
Application Implementations
Multiple Sequencer Implementations
In order to control the sequencing of more than 4 voltages, several of the ISL6123, ISL6124, ISL6125 or ISL6127 devices can be variously configured together to accomplish this. There may be concerns of a particular implementation that would make a particular configuration preferable over another. The fundamental questions to answer to determine which configuration is best suited for your applications are: 1. What level of voltage assurance is needed prior to sequencing on and can the voltage supplies be grouped into high and low criticality? 2. Is there a critical maximum time window all supplies must be present at load or is there a first and a second group preference possibly with some work done in between the two groups of voltages being present?
Three configurations are described and illustrated here. In applications where the integrity of critical voltages must be assured prior to sequencing, additional monitoring of the critical supplies is needed. If the compliance of the voltage is critical for either undervoltage and/or overvoltage, voltage supervisors can be employed to provide this additional assurance across multiple sequencers. Figure 18 is a block diagram of this voltage compliant, high assurance, low risk configuration showing the ISL6131 or ISL6132 supervisor and a mix of FET switched outputs and logic output sequencers (ISL6124 and ISL6125 ICs).
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FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
ISL6131 or 32 MONITORING ON ALL RAILS VMON PGOOD OE LOW = RESET OE LOW = RESET
SYSRST ISL6124 #N UVLO en RESET ENABLE G A T E en
UVLO
SYSRST ISL6124 #N UVLO RESET ENABLE G A T E
ENABLE RESET SYSRST ISL6125 # N+1 POWER SUPPLY RESET UVLO ENABLE L O G I C RESET' SYSRST ISL6125 # N+1 POWER SUPPLY RESET UVLO L O G I C
FIGURE 18. ISL612X AND ISL613X VOLTAGE COMPLIANT SEQUENCING BLOCK DIAGRAM
FIGURE 19. MULTIPLE ISL612X USING LOGIC GATES FOR VOLTAGE PRESENCE DETECT
If the mere presence of some voltage potential is adequate prior to sequencing on, then a small number of standard logic AND gates can be used to accomplish this. The block diagram in Figure 19 illustrates this voltage presence configuration. In either case, the sequencing is straight forward across multiple sequencers as all DLY_ON capacitors will simultaneously start charging ~10ms after the common ENABLE input signal is delivered. This allows the choice of capacitors to be related to each other no different than using a single sequencer. When the common enabling signal is de-asserted these configurations will then execute the turn-off sequence across all sequencers as programmed by the DLY_OFF capacitor values. In both cases, with all the SYSRST pins bussed together, once the on sequence is complete, simultaneous shutdown upon any UVLO input failure is assured as SYSRST output will momentarily pull low turning off all GATE and LOGIC outputs. There may be applications that require or allow groups of supplies being brought up in sequence and supplies within each group to be sequenced. Figure 20 illustrates such a configuration that allows the first group of supplies to turn-on before the second group starts. This arrangement does not necessarily preclude adding the assurance of all supplies prior to turn-on sequencing as previously shown but it will
prevent the turn-on sequence from completing if there is one unsatisfied UVLO input in a group. Using this configuration involves waiting through the TUVLOdel and TRSTdel (total of ~160ms) for each sequencer IC in the chain for the final RESET to release. Once ENABLE on the first sequencer is de-asserted all the RESET outputs will quickly pull low and thus allow the sequenced turn-off of this configuration to ripple through several banks as quickly as the user programmed sequence (as chosen by the DLY_OFF) capacitors allow. Once again with common bussed SYSRTS pins, simultaneous shut down of all GATEs and LOGIC down upon an unsatisfied UVLO input is assured once all FETs or LOGIC output are on. If a GATE drive option IC is used to drive both FETs and logic signals, then care to ensure the charged pump GATE does not overdrive and damage the logic input must be taken. A simple resistor divider can be used to lower the GATE voltage to a suitable voltage for the logic input as shown in Figure 20.
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FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
OE LOW = RESET
SYSRST ISL6124 #N UVLO ENABLE ENABLE RESET
G A T E TO LOGIC INPUT
ENABLE SYSRST
FIGURE 21. OUTPUT VOLTAGE ON LOW TO HIGH TRACKING
ISL6125 # N+1 POWER SUPPLY RESET UVLO RESET L O G I C
RESET
FIGURE 20. MULTIPLE ISL612X SERIAL CONFIGURATION
Voltage Tracking
In some applications the various voltages may have to track each other as they ramp up and down, whereas others may just need sequencing. In these cases, tracking can be accomplished and has been demonstrated over a wide range of load current (1A to 10A) and load capacitance (10F to 3300F) with the ISL612X family. Figure 21 and Figure 22 illustrate output voltage ramping tracking performance. Note that differences are less than 0.5V. With the relevant GATE pins tied together in a star pattern so that the resistance between any two GATE pins is equivalent (1k to 10k), which results in a sharing of the GATE ramping voltage and with the same or similar enough FETs this behavior is observed. It is suggested that this circuit implementation be prototyped and evaluated for the particular expected loads prior to committing to manufacturing build.
FIGURE 22. OUTPUT VOLTAGE HIGH TO LOW TRACKING
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FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Negative Voltage Sequencing
The ISL612X family can use the charged pump GATE output to drive FETs that would control and sequence negative voltages down to a nominal -5V with minimal additional external circuitry. Figure 23 shows turn-on of 5V bipolar supplies together, then the +2.5V and turn-off of both positive supplies being turned off together after the -5V. Figure 24 shows the minimal additional external circuitry to accomplish this. The 5V zener diode is used to level shift the GATE drive down 5V to prevent premature turn-on when GATE = 0V. Once GATE drive voltage > Vz, then FET Vgs > 5V, ensuring full turn-on once GATE gets to VDD+5.3V. Turn-on and turn-off ramp rate can be adjusted with FET gate series resistor value. Sequencing of the -V rail is accomplished as normal via the DLY_X capacitor value although adjustments in prototyping should be factored in to fine tune for actual circuit requirements. Figures 25 and 26 illustrate a high accuracy -V detection circuit using the ISL6131 and a low cost low accuracy -V detect circuit respectively.
R1 VMON R2 +BIAS R3 (1k) +V R5 (10k) Q1 Si1300DL OR EQUIV. TO UVLO OF ISL612X FOR -V CONTROL AND SEQUENCING
ISL6131 OR ISL6536A PGOOD R4 (15K) -BIAS R6
-V
R1 and R2 define -V UVLO level R3 ensures supervisor (ISL6131 or ISL6536A) PGOOD pull-up R4 and R5 provide Q1 gate bias between 0V and +V to 0V (resistor values suitable for -V = -5V and +V = +3.3V) FIGURE 25. HGH ACCURACY -V LOCK OUT
+V
R1 TO UVLO OF ISL612X FOR CONTROL AND SEQUENCING OF -V R2 -V
Chose R1 and R2 values to drive UVLO high when -V is sufficiently present
FIGURE 26. LOW ACCURACY -V PRESENCE DETECTION
Application Considerations
Timing Error Sources
In any system there are variance contributors, for the ISL612X family the timing errors are mainly contributed by three sources.
Capacitor Timing Mismatch Error
Obviously, the absolute capacitor value is an error source, thus lower percentage tolerance capacitors help to reduce this error source. Figure 27 illustrates a difference of 0.57ms between two DLY_X outputs ramping to DLY_X threshold voltage, these 5% capacitors were from a common source. In applications where two or more GATEs or LOGIC outputs must have concurrent transitions, it is recommended that a common GATE drive be used to eliminate this timing error.
FIGURE 23. VOLTAGE SEQUENCING
-VIN
-VOUT
R1 ISL612X GATE D1 ADDITIONAL 2 COMPONENTS NECESSARY FOR -V CONTROL AND SEQUENCING.
D1 necessary to prevent premature turn-on. R1 is used to hold FET Vgs = 0V until D1 Vz is overcome. R1 value can be changed to adjust -V ramp rates. Choose a R1 value between 4M and 10M initially and fine tune resistor value for the particular need. FIGURE 24. -VOLTAGE FET DRIVE CIRCUIT
FIGURE 27. CAPACITOR TIMING MISMATCH
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FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
DLY_X Threshold Voltage and Charging Current Mismatch
The two other error sources come from the IC itself and are the differences in the DLY_X threshold voltage, (DLY_Vth) when the GATE charging latch is set and the DLY_X charging current, (DLY_ichg) across the four individual I/Os. Both of these parameters are bounded by specification and Figure 28 illustrates that with a common capacitor the typical error contributed by these factors is insignificant as both DLY_X traces overlay each other.
FIGURE 28. DLY_VTH AND DLY_ICHG TIMING MISMATCH
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 21
FN9005.10 October 15, 2008
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Package Outline Drawing
L24.4x4
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06
4X 2.5 4.00 A B 19 20X 0.50 24 PIN #1 CORNER (C 0 . 25)
PIN 1 INDEX AREA
18
1
4.00
2 . 10 0 . 15
13
(4X)
0.15 12 7 0.10 M C A B 0 . 07 24X 0 . 23 + 0 . 05 4 24X 0 . 4 0 . 1
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 0 . 1
( 3 . 8 TYP )
C BASE PLANE
SIDE VIEW
SEATING PLANE 0.08 C
(
2 . 10 ) ( 20X 0 . 5 )
C ( 24X 0 . 25 ) ( 24X 0 . 6 )
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
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FN9005.10 October 15, 2008

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